Non-volatile memory is memory that retains its content (data) even when power connected to the memory is turned off. Magnetic random access memory (MRAM) is a type of non-volatile memory. A logical state, or bit, is stored in MRAM by setting magnetic field orientations of MRAM cells within the MRAM. The magnetic field orientations remain even when power to the MRAM cells is turned off.
FIG. 1 shows an MRAM cell 100. The MRAM memory cell 100 includes a soft magnetic region 120, a dielectric region 130 and a hard magnetic region 110. The orientation of magnetization within the soft magnetic region 120 is non-fixed, and can assume two stable orientations as shown by the arrow M1. These two orientations, are either parallel or anti-parallel to the magnetic orientation of the hard magnetic region 110, and determine the logical state of the MRAM memory cell 100. The hard magnetic region 110 (also referred to as a pinned magnetic region) has a fixed magnetic orientation as depicted by the arrow M2. The dielectric region 130 generally provides electrical insulation between the soft magnetic region 120 and the hard magnetic region 110.
The MRAM memory cell is generally located proximate to a crossing point of a word line (WL) and a bit line (BL). The magnetic orientations of the MRAM memory cells are set (written to) by controlling the directions of electrical currents flowing through the word lines and the bit lines, and therefore, by the corresponding magnetic fields induced by the electrical currents. Additionally, the write lines can also be used to read the logic value stored in the memory cells.
The MRAM memory cells are read by sensing a resistance across the MRAM memory cells. The resistance is sensed through the word lines and the bit lines. Generally, the resistance (and therefore, the logical state) of a magnetic memory cell depends on the relative orientations of magnetization in the data layer and the reference layer. For example, the magnetic memory cell is in a state of low resistance if the overall orientation of the magnetization in its data storage layer is parallel to the pinned orientation of magnetization of the reference layer. Conversely, the tunneling junction memory cell is in a high resistance if the overall orientation of magnetization in its data storage layer is anti-parallel to the pinned orientation of magnetization of the reference layer. The magnitude of the switching field required to switch the state of the magnetic memory cells can change over time, further complicating processes for switching the states of the magnetic memory cells.
FIG. 2 shows an array 210 of MRAM memory cells. Bit line and word line selections are made by a row decoder 220 and a column decoder 230, which select a memory cell by conducting current through a selected bit line (BL) and a selected word line (WL). For example, a memory cell 250 is selected by conducting current though a selected bit line 260 and a selected word line 270. The induced magnetic fields should be great enough to reliably set the orientation of magnetization of the selected memory cells of the array of MRAM memory cells 210. The logical states of the memory cells are sensed through corresponding word lines and bit lines by a sense amplifier 240.
The array 210 of MRAM memory cells can suffer from half-select errors when writing to the memory cells. Writing to the memory cells includes selecting a particular bit line (BL), and selecting a particular word line (WL). A half-select error occurs when a memory cell associated with a selected bit line and a non-selected word line changes states, or when a memory cell associated with a non-selected bit line and a selected word line changes states. Clearly, half-select errors degrade the performance of MRAM memory. The write current to the memory cells should be controlled from being so large that excessive half-select errors occur.
The magnitude of applied write current that causes half-select errors can change over time: due to aging and temperature variations. This adds further complexity to writing to an array of magnetic memory cells while minimizing half-select errors.
It is desirable to minimize half-select errors of MRAM memory cells within arrays of MRAM memory cells over time. Additionally, it is desirable ensure that write operations to the MRAM memory cells are consistent and reliable.